Design of a low phase noise, wide output frequency range charge-pump phase-locked loop

• Main Author: Luo, Ying
• Other Authors: Chang Joseph
• Format: Thesis-Master by Coursework
• Language: English
• Published: Nanyang Technological University 2024
• Subjects: Engineering
• Online Access: https://hdl.handle.net/10356/181790
• Institution: Nanyang Technological University

The continuing rapid development of advanced electronic systems, such as that pertaining to next-generation 5G and 6G communications and Artificial Intelligence, demands ever-increasing information transmission speed and data transfer capacity. Within these systems, the Serializer and Deserializer, which is known as the SerDes, is often employed. The phase-locked loop (PLL) is a crucial circuit block in the SerDes – the core frequency provider in SoCs (System-on-Chip) that serves as the clock source for the various sub-systems therein. The Charge Pump PLL (CP-PLL) is widely adopted and typically has a fixed output frequency. When different frequency clock signals are required, multiple PLLs would be needed to work together. This can lead to excessive system power consumption and increased phase noise. In this project, our objective is to design a PLL with a wide frequency range and low phase noise to provide a reliable clock source in around 1 Gbits/s SerDes system. Among the five key modules of the PLL, we focus on the charge pump and voltage-controlled oscillator (VCO). For the charge pump, we propose the adoption of the source-follower switch structure. Compared to the traditional drain-switch structure charge pump, it effectively eliminates the non-ideal factors of charge sharing and charge injection. Additionally, it features lower phase noise and higher linearity. For ring voltage-controlled oscillator, we propose to employ a simpler single-ended structure, which features a wide output frequency range. In contrast, the differential structure of the ring oscillator consumes more power, and can also affect the stability of the loop. To verify the functionality of our PLL circuit, we conduct simulations of the entire circuit by means of Virtuoso software. Based on the TSMC 65nm CMOS process, under a supply voltage of 1.8V and an input reference clock signal of 16MHz, our phase-locked loop can stably generate a specific frequency and the stable locking time of the entire circuit is 22 µs. The simulation results also indicate that the overall phaseIV noise performance is better than conventional low noise PLL circuit, reaching -99.92 dBc@ 1 MHz. This is an improvement of 11% compared to the standard value of -90dBc@ 1 MHz for ordinary low-noise PLL circuits. Further, the output frequency range of our VCO is between 150 MHz and 650 MHz and features an adjustable range of 500MHz. In summary, the design of our charge pump and VCO for a PLL meets our objectives.