Integration of high-κ native oxides of gallium for two-dimensional transistors
The deposition of a metal oxide layer with good dielectric properties is a critical step in fabricating the gate dielectric of transistors based on two-dimensional semiconductors. However, current techniques for depositing ultrathin metal oxide layers on two-dimensional semiconductors suffer from qu...
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sg-ntu-dr.10356-1829412025-03-10T07:06:54Z Integration of high-κ native oxides of gallium for two-dimensional transistors Yi, Kongyang Qin, Wen Huang, Yamin Wu, Yao Feng, Shaopeng Fang, Qiyi Cao, Xun Deng, Ya Zhu, Chao Zou, Xilu Ang, Kah-Wee Li, Taotao Wang, Xinran Lou, Jun Lai, Keji Hu, Zhili Zhang, Zhuhua Dong, Yemin Kalantar-Zadeh, Kourosh Liu, Zheng School of Materials Science and Engineering CINTRA CNRS/NTU/THALES Engineering Dielectrics property Metal oxide layers The deposition of a metal oxide layer with good dielectric properties is a critical step in fabricating the gate dielectric of transistors based on two-dimensional semiconductors. However, current techniques for depositing ultrathin metal oxide layers on two-dimensional semiconductors suffer from quality issues that can compromise transistor performance. Here, we show that an ultrathin and uniform native oxide of gallium (Ga2O3) that naturally forms on the surface of liquid metals in an ambient environment can be prepared on the surface of molybdenum disulfide (MoS2) by squeeze-printing and surface-tension-driven methods. The Ga2O3 layer possesses a high dielectric constant of around 30 and equivalent oxide thickness of around 0.4 nm. Due to the good dielectric properties and van der Waals integration, MoS2 transistors with Ga2O3 gate dielectrics exhibit a subthreshold swing down to 60 mV dec−1, an on/off ratio of 108 and a gate leakage down to around 4 × 10−7 A cm−2. Agency for Science, Technology and Research (A*STAR) National Research Foundation (NRF) Z.L. acknowledges support from the National Research Foundation, Singapore, under its Competitive Research Programme (Grant No. NRF-CRP22-2019-0007) and its NRF-ISF joint research program (Grant No. NRF2020-NRF-ISF004-3520). This research is also supported by A*STAR under an AME IRG grant (Project No. A2083c0052) and A*STAR MTC Programmatic Grant (Grant No. M23M2b0056). The microwave microscopy work (S.F. and K.L.) is supported by the Welch Foundation (Grant No. F-1814). The nanoindentation work (Q.F. and J.L) is supported by the Welch Foundation (Grant No. C-1716). 2025-03-10T07:06:54Z 2025-03-10T07:06:54Z 2024 Journal Article Yi, K., Qin, W., Huang, Y., Wu, Y., Feng, S., Fang, Q., Cao, X., Deng, Y., Zhu, C., Zou, X., Ang, K., Li, T., Wang, X., Lou, J., Lai, K., Hu, Z., Zhang, Z., Dong, Y., Kalantar-Zadeh, K. & Liu, Z. (2024). Integration of high-κ native oxides of gallium for two-dimensional transistors. Nature Electronics, 7(12), 1126-1136. https://dx.doi.org/10.1038/s41928-024-01286-x 2520-1131 https://hdl.handle.net/10356/182941 10.1038/s41928-024-01286-x 2-s2.0-85209131988 12 7 1126 1136 en NRF-CRP22-2019-0007 NRF2020-NRF-ISF004-3520 A2083c0052 M23M2b0056 Nature Electronics © 2024 The Author(s), under exclusive licence to Springer Nature Limited. All rights reserved. |
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Engineering Dielectrics property Metal oxide layers Yi, Kongyang Qin, Wen Huang, Yamin Wu, Yao Feng, Shaopeng Fang, Qiyi Cao, Xun Deng, Ya Zhu, Chao Zou, Xilu Ang, Kah-Wee Li, Taotao Wang, Xinran Lou, Jun Lai, Keji Hu, Zhili Zhang, Zhuhua Dong, Yemin Kalantar-Zadeh, Kourosh Liu, Zheng Integration of high-κ native oxides of gallium for two-dimensional transistors |
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The deposition of a metal oxide layer with good dielectric properties is a critical step in fabricating the gate dielectric of transistors based on two-dimensional semiconductors. However, current techniques for depositing ultrathin metal oxide layers on two-dimensional semiconductors suffer from quality issues that can compromise transistor performance. Here, we show that an ultrathin and uniform native oxide of gallium (Ga2O3) that naturally forms on the surface of liquid metals in an ambient environment can be prepared on the surface of molybdenum disulfide (MoS2) by squeeze-printing and surface-tension-driven methods. The Ga2O3 layer possesses a high dielectric constant of around 30 and equivalent oxide thickness of around 0.4 nm. Due to the good dielectric properties and van der Waals integration, MoS2 transistors with Ga2O3 gate dielectrics exhibit a subthreshold swing down to 60 mV dec−1, an on/off ratio of 108 and a gate leakage down to around 4 × 10−7 A cm−2. |
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School of Materials Science and Engineering |
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School of Materials Science and Engineering Yi, Kongyang Qin, Wen Huang, Yamin Wu, Yao Feng, Shaopeng Fang, Qiyi Cao, Xun Deng, Ya Zhu, Chao Zou, Xilu Ang, Kah-Wee Li, Taotao Wang, Xinran Lou, Jun Lai, Keji Hu, Zhili Zhang, Zhuhua Dong, Yemin Kalantar-Zadeh, Kourosh Liu, Zheng |
format |
Article |
author |
Yi, Kongyang Qin, Wen Huang, Yamin Wu, Yao Feng, Shaopeng Fang, Qiyi Cao, Xun Deng, Ya Zhu, Chao Zou, Xilu Ang, Kah-Wee Li, Taotao Wang, Xinran Lou, Jun Lai, Keji Hu, Zhili Zhang, Zhuhua Dong, Yemin Kalantar-Zadeh, Kourosh Liu, Zheng |
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Yi, Kongyang |
title |
Integration of high-κ native oxides of gallium for two-dimensional transistors |
title_short |
Integration of high-κ native oxides of gallium for two-dimensional transistors |
title_full |
Integration of high-κ native oxides of gallium for two-dimensional transistors |
title_fullStr |
Integration of high-κ native oxides of gallium for two-dimensional transistors |
title_full_unstemmed |
Integration of high-κ native oxides of gallium for two-dimensional transistors |
title_sort |
integration of high-κ native oxides of gallium for two-dimensional transistors |
publishDate |
2025 |
url |
https://hdl.handle.net/10356/182941 |
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1826362247908163584 |