Analog circuit layout design based on cadence virtuoso and calibre

• المؤلف الرئيسي: Bai, Jiaming
• مؤلفون آخرون: Tang Xiaohong
• التنسيق: Thesis-Master by Coursework
• اللغة: English
• منشور في: Nanyang Technological University 2025
• الموضوعات: Engineering; Amplifier design; Analog layout; Parasitic effects; Layout-dependent effects; Square layout; Tap cells
• الوصول للمادة أونلاين: https://hdl.handle.net/10356/183066

This thesis examines the utilization of semiconductor physics in analog circuit design, specifically highlighting amplifier layout design and its related issues. Beginning with essential semiconductor principles, it examines the impacts of doping, carrier transport, and band structure on device efficacy, establishing a robust theoretical basis for future device and circuit design. The paper analyzes the properties and applications of MOSFETs and their advanced versions, including FinFETs, within the realm of device technology. Investigations are conducted on techniques including high K/metal gate integration, fully depleted architectures, and mechanical stress optimization to address the performance requirements of advanced process nodes. The layout design inside the ADC is the main emphasis of the amplifier design component of this study. The study closely looks at fundamental procedures including component placement, signal path optimization, and symmetry variables. The study highlights the benefits of square layouts, especially in terms of increased production efficiency and signal integrity. The role of tap changers in power regulation and noise reduction is also covered. We investigate layout-dependent effects (LDEs), such as matching accuracy and parasite affects. Additionally, optimization strategies, including co-centering and parasite extraction tools, are suggested to enhance reliability and performance. This thesis provides a detailed examination of high-precision analog circuit layout, integrating theoretical insights with practical applications. It focuses on enhancing amplifier performance and circuit reliability. Future research will investigate the challenges and solutions associated with analog circuit design in the context of deep submicron fabrication nodes.