Analog circuit layout design based on cadence virtuoso and calibre

• المؤلف الرئيسي: Bai, Jiaming
• مؤلفون آخرون: Tang Xiaohong
• التنسيق: Thesis-Master by Coursework
• اللغة: English
• منشور في: Nanyang Technological University 2025
• الموضوعات: Engineering; Amplifier design; Analog layout; Parasitic effects; Layout-dependent effects; Square layout; Tap cells
• الوصول للمادة أونلاين: https://hdl.handle.net/10356/183066
• المؤسسة: Nanyang Technological University

This thesis examines the utilization of semiconductor physics in analog circuit design, specifically highlighting amplifier layout design and its related issues. Beginning with essential semiconductor principles, it examines the impacts of doping, carrier transport, and band structure on device effi...