Feasibility studies of high data rate ADC
In the design project, a 2-bit flash ADC stage has been developed. All the functional blocks are investigated and optimized according the design specifications. The proposed fully differential double-sampled sample and hold circuit with low pedestal error and a fully differential dynamic latch compa...
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| Format: | Final Year Project |
| Language: | English |
| Published: |
2009
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| Subjects: | |
| Online Access: | http://hdl.handle.net/10356/18375 |
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| Institution: | Nanyang Technological University |
| Language: | English |
| Summary: | In the design project, a 2-bit flash ADC stage has been developed. All the functional blocks are investigated and optimized according the design specifications. The proposed fully differential double-sampled sample and hold circuit with low pedestal error and a fully differential dynamic latch comparator are modified in order to meet the criterions. In particular, the design of the two-stage high speed operational-amplifier has been carried out in transistor level. This operational amplifier is design base on the specification stated in the project; a dedicated fast comparator with fully differential dynamic latch is used to achieve high speed input sample comparisons; a compensated decoder logic circuit is used to produce stable and accurate binary output codes. Testing and simulations are performed for each individual functional block as well as the overall system. It has been demonstrated that the ADC design specifications are properly met. More over, some performance merits such as high speed, high accuracy and low noise are also observed in the final design. |
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