High speed prescaler for bluetooth application

Capitalizing on the human insatiable need for information, many consumer products has incorporated wireless standards such as IEEE 80211, Bluetooth and Zigbee to allow for rapid information exchange even on the go. The original intent of allowing the user to be connected everywhere he/she goes impl...

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Main Author: Chu, Dennis Wah Tat.
Other Authors: Goh Wang Ling
Format: Theses and Dissertations
Language:English
Published: 2009
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Online Access:http://hdl.handle.net/10356/18768
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Institution: Nanyang Technological University
Language: English
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spelling sg-ntu-dr.10356-187682023-07-04T15:22:26Z High speed prescaler for bluetooth application Chu, Dennis Wah Tat. Goh Wang Ling School of Electrical and Electronic Engineering Centre for Integrated Circuits and Systems DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits Capitalizing on the human insatiable need for information, many consumer products has incorporated wireless standards such as IEEE 80211, Bluetooth and Zigbee to allow for rapid information exchange even on the go. The original intent of allowing the user to be connected everywhere he/she goes implies that the product has to be portable. The portability translates into limited real estate for the energy source and circuitry. To combat this, many development groups sought to realize a fully integrated transceiver capable of low power operation. The focal point when tackling the transceiver’s power consumption is the frequency synthesizer which is usually formed by a Phase-Locked Loop (PLL) since it accounts for a majority of the total power consumed. The performance in power consumption and channel selection of the frequency synthesizer are limited by the frequency divider and voltage-controlled oscillator (VCO). The objective of this work is to design a Divide-by-15/16 Prescaler which can be then integrated in an N- Divider for Bluetooth application. The Prescaler will be realized using Chartered Semiconductor Manufacturing Limited CMOS technology (0.18-μm CMOS process). The power consumption reduction and speed enhancement are realized through the use of asynchronous and synchronous logic for the overall division and usage of dynamic circuit technique in designing the D Flip-Flop using in the division. The dynamic CMOS divide-by- 15/16 Prescaler is implemented in this project. The design is based upon the True Single Phase Clock (TSPC) and Extended True Single Phase Clock (E-TSPC) techniques. The power consumption achieved is 3.3 mW, at a supply voltage of 1.8 V. Master of Science (Integrated Circuit Design) 2009-07-17T07:43:47Z 2009-07-17T07:43:47Z 2008 2008 Thesis http://hdl.handle.net/10356/18768 en 49 p. application/pdf
institution Nanyang Technological University
building NTU Library
continent Asia
country Singapore
Singapore
content_provider NTU Library
collection DR-NTU
language English
topic DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
spellingShingle DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
Chu, Dennis Wah Tat.
High speed prescaler for bluetooth application
description Capitalizing on the human insatiable need for information, many consumer products has incorporated wireless standards such as IEEE 80211, Bluetooth and Zigbee to allow for rapid information exchange even on the go. The original intent of allowing the user to be connected everywhere he/she goes implies that the product has to be portable. The portability translates into limited real estate for the energy source and circuitry. To combat this, many development groups sought to realize a fully integrated transceiver capable of low power operation. The focal point when tackling the transceiver’s power consumption is the frequency synthesizer which is usually formed by a Phase-Locked Loop (PLL) since it accounts for a majority of the total power consumed. The performance in power consumption and channel selection of the frequency synthesizer are limited by the frequency divider and voltage-controlled oscillator (VCO). The objective of this work is to design a Divide-by-15/16 Prescaler which can be then integrated in an N- Divider for Bluetooth application. The Prescaler will be realized using Chartered Semiconductor Manufacturing Limited CMOS technology (0.18-μm CMOS process). The power consumption reduction and speed enhancement are realized through the use of asynchronous and synchronous logic for the overall division and usage of dynamic circuit technique in designing the D Flip-Flop using in the division. The dynamic CMOS divide-by- 15/16 Prescaler is implemented in this project. The design is based upon the True Single Phase Clock (TSPC) and Extended True Single Phase Clock (E-TSPC) techniques. The power consumption achieved is 3.3 mW, at a supply voltage of 1.8 V.
author2 Goh Wang Ling
author_facet Goh Wang Ling
Chu, Dennis Wah Tat.
format Theses and Dissertations
author Chu, Dennis Wah Tat.
author_sort Chu, Dennis Wah Tat.
title High speed prescaler for bluetooth application
title_short High speed prescaler for bluetooth application
title_full High speed prescaler for bluetooth application
title_fullStr High speed prescaler for bluetooth application
title_full_unstemmed High speed prescaler for bluetooth application
title_sort high speed prescaler for bluetooth application
publishDate 2009
url http://hdl.handle.net/10356/18768
_version_ 1772826280641691648