CMOS capacitor multiplier

• المؤلف الرئيسي: Mirea Iulian.
• مؤلفون آخرون: Chan Pak Kwong
• التنسيق: Theses and Dissertations
• اللغة: English
• منشور في: 2009
• الموضوعات: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
• الوصول للمادة أونلاين: http://hdl.handle.net/10356/18813
• المؤسسة: Nanyang Technological University

A new circuit topology for a grounded capacitor multiplier has been proposed. The main goal is to practically implement a high multiplication factor for capacitance in view of device mismatching and power consumption. Power by a supply of 3.3 V, the proposed circuit is implemented using CSM CMOS 0....