CMOS capacitor multiplier
A new circuit topology for a grounded capacitor multiplier has been proposed. The main goal is to practically implement a high multiplication factor for capacitance in view of device mismatching and power consumption. Power by a supply of 3.3 V, the proposed circuit is implemented using CSM CMOS 0....
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| 格式: | Theses and Dissertations |
| 語言: | English |
| 出版: |
2009
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| 主題: | |
| 在線閱讀: | http://hdl.handle.net/10356/18813 |
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| 機構: | Nanyang Technological University |
| 語言: | English |