Development of a chip-on-tape encapsulation process

Development of a chip-on-tape encapsulation process

This thesis summarizes the work conducted in an effort to develop an encapsulation process for a chip-on-tape package. The various studies conducted included encapsulation material selection, encapsulation process studies and optimization and FEA simulations for the prediction of package performance...

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Bibliographic Details
Main Author: Mui, Yew Cheong.
Other Authors: Tan, Soo Lip
Format: Theses and Dissertations
Language:English
Published: 2009
Subjects:
DRNTU::Engineering::Manufacturing::Product engineering
Online Access:http://hdl.handle.net/10356/20541
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Institution: Nanyang Technological University
Language: English
id sg-ntu-dr.10356-20541
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spelling sg-ntu-dr.10356-205412020-09-26T22:14:39Z Development of a chip-on-tape encapsulation process Mui, Yew Cheong. Tan, Soo Lip Gintic Institute of Manufacturing Technology DRNTU::Engineering::Manufacturing::Product engineering This thesis summarizes the work conducted in an effort to develop an encapsulation process for a chip-on-tape package. The various studies conducted included encapsulation material selection, encapsulation process studies and optimization and FEA simulations for the prediction of package performance. Reliability tests which included temperature cycle test and high temperature- high humidity test were also conducted in the material selection phase. Master of Science (Precision Engineering) 2009-12-15T03:17:38Z 2009-12-15T03:17:38Z 1996 1996 Thesis http://hdl.handle.net/10356/20541 en NANYANG TECHNOLOGICAL UNIVERSITY 79 p. application/pdf
institution Nanyang Technological University
building NTU Library
country Singapore
collection DR-NTU
language English
topic DRNTU::Engineering::Manufacturing::Product engineering
spellingShingle DRNTU::Engineering::Manufacturing::Product engineering
Mui, Yew Cheong.
Development of a chip-on-tape encapsulation process
description This thesis summarizes the work conducted in an effort to develop an encapsulation process for a chip-on-tape package. The various studies conducted included encapsulation material selection, encapsulation process studies and optimization and FEA simulations for the prediction of package performance. Reliability tests which included temperature cycle test and high temperature- high humidity test were also conducted in the material selection phase.
author2 Tan, Soo Lip
author_facet Tan, Soo Lip
Mui, Yew Cheong.
format Theses and Dissertations
author Mui, Yew Cheong.
author_sort Mui, Yew Cheong.
title Development of a chip-on-tape encapsulation process
title_short Development of a chip-on-tape encapsulation process
title_full Development of a chip-on-tape encapsulation process
title_fullStr Development of a chip-on-tape encapsulation process
title_full_unstemmed Development of a chip-on-tape encapsulation process
title_sort development of a chip-on-tape encapsulation process
publishDate 2009
url http://hdl.handle.net/10356/20541
_version_ 1681059572252409856

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