Low power VLSI design

Focuses on the design of a new class of circuits which can overcome the CV2f barrier faced by the conventional CMOS logic.

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Bibliographic Details
Main Author: Yeo, Kiat Seng
Other Authors: School of Electrical and Electronic Engineering
Format: Research Report
Published: 2008
Subjects:
Online Access:http://hdl.handle.net/10356/2687
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Institution: Nanyang Technological University
id sg-ntu-dr.10356-2687
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spelling sg-ntu-dr.10356-26872023-03-04T03:23:52Z Low power VLSI design Yeo, Kiat Seng School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits Focuses on the design of a new class of circuits which can overcome the CV2f barrier faced by the conventional CMOS logic. RGM 16/97 2008-09-17T09:13:08Z 2008-09-17T09:13:08Z 2000 2000 Research Report http://hdl.handle.net/10356/2687 Nanyang Technological University application/pdf
institution Nanyang Technological University
building NTU Library
continent Asia
country Singapore
Singapore
content_provider NTU Library
collection DR-NTU
topic DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
spellingShingle DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
Yeo, Kiat Seng
Low power VLSI design
description Focuses on the design of a new class of circuits which can overcome the CV2f barrier faced by the conventional CMOS logic.
author2 School of Electrical and Electronic Engineering
author_facet School of Electrical and Electronic Engineering
Yeo, Kiat Seng
format Research Report
author Yeo, Kiat Seng
author_sort Yeo, Kiat Seng
title Low power VLSI design
title_short Low power VLSI design
title_full Low power VLSI design
title_fullStr Low power VLSI design
title_full_unstemmed Low power VLSI design
title_sort low power vlsi design
publishDate 2008
url http://hdl.handle.net/10356/2687
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