Low power VLSI design

• 主要作者: Yeo, Kiat Seng
• 其他作者: School of Electrical and Electronic Engineering
• 格式: Research Report
• 出版: 2008
• 主題: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
• 在線閱讀: http://hdl.handle.net/10356/2687
• 機構: Nanyang Technological University

Focuses on the design of a new class of circuits which can overcome the CV2f barrier faced by the conventional CMOS logic.