Post stress reliability in submicron MOSFET devices

Post stress reliability in submicron MOSFET devices

In this project, we have conducted a systematic investigation of post-breakdown conduction and its instability in ultrathin SiO2 films as well as various studies of interface degradation, charge trapping and oxide barrier height change in deep submicron MOS devices with ultrathin gate oxide caused b...

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Main Authors: Chen, Tupei., Tse, Man Siu.
Other Authors: School of Electrical and Electronic Engineering
Format: Research Report
Published: 2008
Subjects:
DRNTU::Engineering::Electrical and electronic engineering::Semiconductors
Online Access:http://hdl.handle.net/10356/2834
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Institution: Nanyang Technological University
id sg-ntu-dr.10356-2834
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spelling sg-ntu-dr.10356-28342023-03-04T03:23:17Z Post stress reliability in submicron MOSFET devices Chen, Tupei. Tse, Man Siu. School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering::Semiconductors In this project, we have conducted a systematic investigation of post-breakdown conduction and its instability in ultrathin SiO2 films as well as various studies of interface degradation, charge trapping and oxide barrier height change in deep submicron MOS devices with ultrathin gate oxide caused by electrical stress. RG 52/96 2008-09-17T09:15:20Z 2008-09-17T09:15:20Z 2002 2002 Research Report http://hdl.handle.net/10356/2834 Nanyang Technological University application/pdf
institution Nanyang Technological University
building NTU Library
continent Asia
country Singapore
Singapore
content_provider NTU Library
collection DR-NTU
topic DRNTU::Engineering::Electrical and electronic engineering::Semiconductors
spellingShingle DRNTU::Engineering::Electrical and electronic engineering::Semiconductors
Chen, Tupei.
Tse, Man Siu.
Post stress reliability in submicron MOSFET devices
description In this project, we have conducted a systematic investigation of post-breakdown conduction and its instability in ultrathin SiO2 films as well as various studies of interface degradation, charge trapping and oxide barrier height change in deep submicron MOS devices with ultrathin gate oxide caused by electrical stress.
author2 School of Electrical and Electronic Engineering
author_facet School of Electrical and Electronic Engineering
Chen, Tupei.
Tse, Man Siu.
format Research Report
author Chen, Tupei.
Tse, Man Siu.
author_sort Chen, Tupei.
title Post stress reliability in submicron MOSFET devices
title_short Post stress reliability in submicron MOSFET devices
title_full Post stress reliability in submicron MOSFET devices
title_fullStr Post stress reliability in submicron MOSFET devices
title_full_unstemmed Post stress reliability in submicron MOSFET devices
title_sort post stress reliability in submicron mosfet devices
publishDate 2008
url http://hdl.handle.net/10356/2834
_version_ 1759856563569295360

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