Low power CMOS circuit design using adiabatic logic

• Main Author: Parthasarathy Srinivasa Raghavan.
• Other Authors: Lau Kim Teen
• Format: Theses and Dissertations
• Published: 2008
• Subjects: DRNTU::Engineering::Electrical and electronic engineering
• Online Access: http://hdl.handle.net/10356/3114
• Institution: Nanyang Technological University

This dissertation elaborated on the most popular low power CMOS circuit and power reduction techniques. A special punch is given on the Adiabatic Quasi-Static CMOS logic of power reduction, followed by the proposal of “Reduced swing Aqs-CMOS/ASL logic.