Layout design for input/output transistors
In this project, the performance of area-efficient CMOS buffers using the octagon-type and circle-type layout for both NMOS and PMOS transistors are investigated. The performance criteria include the efficient use of layout area, output driving/ sinking capability and ESD robustness.
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sg-ntu-dr.10356-37572023-07-04T15:21:36Z Layout design for input/output transistors Wong, David Wing Fatt. Yeo, Kiat Seng School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits In this project, the performance of area-efficient CMOS buffers using the octagon-type and circle-type layout for both NMOS and PMOS transistors are investigated. The performance criteria include the efficient use of layout area, output driving/ sinking capability and ESD robustness. Master of Science (Consumer Electronics) 2008-09-17T09:36:55Z 2008-09-17T09:36:55Z 2001 2001 Thesis http://hdl.handle.net/10356/3757 Nanyang Technological University application/pdf |
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DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits Wong, David Wing Fatt. Layout design for input/output transistors |
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In this project, the performance of area-efficient CMOS buffers using the octagon-type and circle-type layout for both NMOS and PMOS transistors are investigated. The performance criteria include the efficient use of layout area, output driving/ sinking capability and ESD robustness. |
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Yeo, Kiat Seng |
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Yeo, Kiat Seng Wong, David Wing Fatt. |
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Theses and Dissertations |
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Wong, David Wing Fatt. |
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Wong, David Wing Fatt. |
title |
Layout design for input/output transistors |
title_short |
Layout design for input/output transistors |
title_full |
Layout design for input/output transistors |
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Layout design for input/output transistors |
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Layout design for input/output transistors |
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layout design for input/output transistors |
publishDate |
2008 |
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http://hdl.handle.net/10356/3757 |
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1772827908439539712 |