Design and analysis of redundant binary booth multipliers
Multiplication is a fundamental operation in most arithmetic computing systems. Over the last few decades, Redundant Binary (RB) number has emerged as a key internal format to speed up the partial product accumulation of treestructured parallel multipliers due to its carry-free property and regulari...
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sg-ntu-dr.10356-414122023-07-04T16:53:09Z Design and analysis of redundant binary booth multipliers He, Ya Juan Chang Chip Hong School of Electrical and Electronic Engineering Centre for Integrated Circuits and Systems DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits Multiplication is a fundamental operation in most arithmetic computing systems. Over the last few decades, Redundant Binary (RB) number has emerged as a key internal format to speed up the partial product accumulation of treestructured parallel multipliers due to its carry-free property and regularity in Very Large Scale Integrated (VLSI) implementation. In this thesis, the high performance energy-efficient multiplication operation has been investigated based on three key constituent components of the RB Booth multiplier architecture. DOCTOR OF PHILOSOPHY (EEE) 2010-07-02T07:13:25Z 2010-07-02T07:13:25Z 2008 2008 Thesis He, Y. J. (2008). Design and analysis of redundant binary booth multipliers. Doctoral thesis, Nanyang Technological University, Singapore. https://hdl.handle.net/10356/41412 10.32657/10356/41412 en 178 p. application/pdf |
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DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits |
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DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits He, Ya Juan Design and analysis of redundant binary booth multipliers |
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Multiplication is a fundamental operation in most arithmetic computing systems. Over the last few decades, Redundant Binary (RB) number has emerged as a key internal format to speed up the partial product accumulation of treestructured parallel multipliers due to its carry-free property and regularity in
Very Large Scale Integrated (VLSI) implementation. In this thesis, the high
performance energy-efficient multiplication operation has been investigated based on three key constituent components of the RB Booth multiplier architecture. |
| author2 |
Chang Chip Hong |
| author_facet |
Chang Chip Hong He, Ya Juan |
| format |
Theses and Dissertations |
| author |
He, Ya Juan |
| author_sort |
He, Ya Juan |
| title |
Design and analysis of redundant binary booth multipliers |
| title_short |
Design and analysis of redundant binary booth multipliers |
| title_full |
Design and analysis of redundant binary booth multipliers |
| title_fullStr |
Design and analysis of redundant binary booth multipliers |
| title_full_unstemmed |
Design and analysis of redundant binary booth multipliers |
| title_sort |
design and analysis of redundant binary booth multipliers |
| publishDate |
2010 |
| url |
https://hdl.handle.net/10356/41412 |
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1772826381133021184 |