VLSI implementation of Reed Solomon encoder and decoder chip

VLSI implementation of Reed Solomon encoder and decoder chip

This report represents the VLSI design implementation of the Reed Solomon Encoder and Decoder. The overall architecture, design, simulation and synthesis of the Reed Solomon Encoder and Decoder, as well as the internal modules are discussed in detail.

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Bibliographic Details
Main Author: Lau, Luh Chyuan.
Other Authors: Ho, Duan Juat
Format: Theses and Dissertations
Published: 2008
Subjects:
DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
Online Access:http://hdl.handle.net/10356/4561
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Institution: Nanyang Technological University
Description
Summary:This report represents the VLSI design implementation of the Reed Solomon Encoder and Decoder. The overall architecture, design, simulation and synthesis of the Reed Solomon Encoder and Decoder, as well as the internal modules are discussed in detail.

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