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VLSI implementation of Reed Solomon encoder and decoder chip

This report represents the VLSI design implementation of the Reed Solomon Encoder and Decoder. The overall architecture, design, simulation and synthesis of the Reed Solomon Encoder and Decoder, as well as the internal modules are discussed in detail.

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書目詳細資料
主要作者: Lau, Luh Chyuan.
其他作者: Ho, Duan Juat
格式: Theses and Dissertations
出版: 2008
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在線閱讀:http://hdl.handle.net/10356/4561
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