Low-power comparator-based pipelined ADC
Technology scaling has caused many issues for analog design. The op-amp based pipelined ADC which using the charge transfer technique using high gain, high speed manner had become an issue when the scaling down of device size and supply voltage occur. This project study a comparator based pipelined...
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| 主要作者: | |
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| 格式: | Final Year Project |
| 語言: | English |
| 出版: |
2011
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| 主題: | |
| 在線閱讀: | http://hdl.handle.net/10356/46011 |
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| 機構: | Nanyang Technological University |
| 語言: | English |
| 總結: | Technology scaling has caused many issues for analog design. The op-amp based pipelined ADC which using the charge transfer technique using high gain, high speed manner had become an issue when the scaling down of device size and supply voltage occur. This project study a comparator based pipelined ADC which uses a zero crossing detector circuit for special case comparator. By using the zero crossing detector circuit, this circuit claim to have high speed, low power and suitable to be used in a 0.18um technology with 1.8V power supply. This report include the result of simulation of the comparator based pipelined ADC using a zero crossing detector under cadence environment with CSM018IC technology. |
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