Design and analysis of class-E power amplifier
In this paper, based on the specification assigned, I have designed a low voltage Class-E Power Amplifier (PA) using the 0.18μm TSMC CMOS technology from BSIM3 model to achieve the following results: f = 5.8GHz, Pout = 13.003dBm, VDD = 1.8VDC, Bandwidth = 200MHz, Termination = 50Ω, Power Added E...
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| Format: | Final Year Project |
| Language: | English |
| Published: |
2011
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| Subjects: | |
| Online Access: | http://hdl.handle.net/10356/46198 |
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| Institution: | Nanyang Technological University |
| Language: | English |
| Summary: | In this paper, based on the specification assigned, I have designed a low voltage Class-E Power Amplifier (PA) using the 0.18μm TSMC CMOS technology from BSIM3 model to achieve the following results:
f = 5.8GHz, Pout = 13.003dBm, VDD = 1.8VDC, Bandwidth = 200MHz, Termination = 50Ω, Power Added Efficiency = 71.3%.
The design of Class-E PA network contains the presence of parasitics and losses in the switch and shunt-capacitor. The transistor will provide an optimum PAE (power added efficiency).
Lastly, the design is simulated and fine-tuning to it resonant to achieve the maximum power control capabilities. |
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