Design methodologies for low-power asynchronous-logic digital systems
250 p.
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2011
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sg-ntu-dr.10356-470342023-07-04T16:19:13Z Design methodologies for low-power asynchronous-logic digital systems Law, Chong Fatt Joseph Chang Gwee Bah Hwee School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering 250 p. Asynchronous design has been an active area of research since the 1950s, but has hitherto yet to achieve widespread use or acceptance. This is largely because several major problems continue to persist that inhibit its acceptance in the very large-scale integration industry as a viable alternative to the prevalent synchronous design. This thesis addresses one such problem: how to reduce the circuit area and power dissipation of asynchronous control networks. DOCTOR OF PHILOSOPHY (EEE) 2011-12-27T05:56:28Z 2011-12-27T05:56:28Z 2008 2008 Thesis Law, C. F. (2008). Design methodologies for low-power asynchronous-logic digital systems. Doctoral thesis, Nanyang Technological University, Singapore. https://hdl.handle.net/10356/47034 10.32657/10356/47034 Nanyang Technological University application/pdf |
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Asia |
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Singapore Singapore |
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DRNTU::Engineering::Electrical and electronic engineering |
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DRNTU::Engineering::Electrical and electronic engineering Law, Chong Fatt Design methodologies for low-power asynchronous-logic digital systems |
| description |
250 p. |
| author2 |
Joseph Chang |
| author_facet |
Joseph Chang Law, Chong Fatt |
| format |
Theses and Dissertations |
| author |
Law, Chong Fatt |
| author_sort |
Law, Chong Fatt |
| title |
Design methodologies for low-power asynchronous-logic digital systems |
| title_short |
Design methodologies for low-power asynchronous-logic digital systems |
| title_full |
Design methodologies for low-power asynchronous-logic digital systems |
| title_fullStr |
Design methodologies for low-power asynchronous-logic digital systems |
| title_full_unstemmed |
Design methodologies for low-power asynchronous-logic digital systems |
| title_sort |
design methodologies for low-power asynchronous-logic digital systems |
| publishDate |
2011 |
| url |
https://hdl.handle.net/10356/47034 |
| _version_ |
1772826770328780800 |