ASIC implementation of a high speed data scaler for residue number system
Unconventional number system, the Residue Number System (RNS) is introduced for its efficient arithmetic operations such as addition, subtraction and multiplication as long operations are broken down into several shorter and independent operations without carry propagation between them. How...
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| Format: | Final Year Project |
| Language: | English |
| Published: |
2012
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| Subjects: | |
| Online Access: | http://hdl.handle.net/10356/49912 |
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| Institution: | Nanyang Technological University |
| Language: | English |
| Summary: | Unconventional number system, the Residue Number System (RNS) is introduced
for its efficient arithmetic operations such as addition, subtraction and multiplication
as long operations are broken down into several shorter and independent operations
without carry propagation between them. However, scaling, an essential operation in
digital signal processing remained as one of the bottleneck of RNS which hinder the
wider adoption of RNS due to its non-weighted characteristic.In this project, the architecture of the new proposed scaling algorithm for the
programmable scaler is coded and synthesized. The placement and routing of this
new RNS design, combining with other designs is also performed using the
Cadence® SoC Encounter™ RTL-to-GDSII System version 8.1. Lastly, testing
circuitry is also developed to test the functionality of the chip after being fabricated. |
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