Embedded logic compatible dynamic random access memory design

• Main Author: Yi, He.
• Other Authors: School of Electrical and Electronic Engineering
• Format: Final Year Project
• Language: English
• Published: 2012
• Subjects: DRNTU::Engineering::Electrical and electronic engineering
• Online Access: http://hdl.handle.net/10356/49934
• Institution: Nanyang Technological University

Logic-compatible 2T and 3T embedded DRAM (EDRAM) cells have recently gained their popularity in embedded applications because of their high density and good voltage margin. The most important design requirements in EDRAM cells are the cell area, data retention time and read speed. In the first part of this FYP, an in-depth analysis on the leakage mechanism and hence the retention time of the cells are carried out, followed by the impacts of several design factors (W, L, biasing voltage, and temperature). Finally, a systematic methodology is proposed for enhancing the retention time of the cell. Two representative EDRAM cells have been used to demonstrate the methodology. Simulation result using a standard 65 nm process shows that the data retention time is improved by more than 2.5X after optimization. In the second part of the report, the system level analysis is carried by using 128cells/column array and 256cells/column array, few techniques are proposed to further enhance the cell retention time and the cell performance, the comparison to the existing EDRAM cell design are also carried out.