Design of low-power and low-voltage VLSI multipliers

This thesis proposes several designs for low-power low-voltage digital CMOS multipliers for two's complement multiplication.

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Bibliographic Details
Main Author:	Ong, Geok Ling.
Other Authors:	Liu, Po-Ching
Format:	Theses and Dissertations
Published:	2008
Subjects:	DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
Online Access:	http://hdl.handle.net/10356/4997
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Institution:	Nanyang Technological University

Description
Summary:	This thesis proposes several designs for low-power low-voltage digital CMOS multipliers for two's complement multiplication.

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