Design of low-power and low-voltage VLSI multipliers

• المؤلف الرئيسي: Ong, Geok Ling.
• مؤلفون آخرون: Liu, Po-Ching
• التنسيق: Theses and Dissertations
• منشور في: 2008
• الموضوعات: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
• الوصول للمادة أونلاين: http://hdl.handle.net/10356/4997

This thesis proposes several designs for low-power low-voltage digital CMOS multipliers for two's complement multiplication.