Frequency multiplier for 120 GHz signal source

• Main Author: Wang, Yong.
• Other Authors: School of Electrical and Electronic Engineering
• Format: Theses and Dissertations
• Language: English
• Published: 2013
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
• Online Access: http://hdl.handle.net/10356/51324
• Institution: Nanyang Technological University

According to the International Technology Roadmap for Semiconductors, silicon-based semiconductor processes are opening doors for millimeter-wave and Terahertz (THz) applications in integrated circuits. Stable and precise millimeter-wave and THz frequency sources are the key and challenging components for the aforementioned high frequency systems. The scope of this thesis is to design frequency multipliers with high efficiency and multiplication factor to multiply the fundamental signal of the frequency phase-locked loop (PLL). The multiplier cores in prior PLLs employ methods of Class-B/C amplifier, mixer, linear superposition technique and travelling-wave multiplier. These techniques present low power efficiency, low conversion efficiency, low output power and small multiplication factor. Suffering from these drawbacks, several multiplier cores are required to be cascaded to achieve a high multiplication factor. Additional power amplifiers are also indispensable among the stages to compensate for the power losses. These solutions inevitably lead to larger system and greater power consumption. This thesis presents a novel phase-controlled multi-push technique that can directly synthesize the Nth harmonic to achieve not just superior power efficiency but also boosting the power efficiency to 50% in an ideal situation. The proposed phase-controlled multi-push multiplier generates harmonics by adding the outputs of the proposed W-shaping phase-controlled cascodes. The W-shaping phase-controlled cascode is a basic element of the phase-controlled multi-push multiplier that generates output waveform shaped like the alphabet "W". The proposed approach had been applied to construct both a tripler and a quadrupler. The two circuits had proven the concept and verified their operating conditions, and will be detailed in this thesis. A 121-to-137 GHz frequency quadrupler based on the proposed phase-controlled multi-push technique was demonstrated using a 0.13-m SiGe BiCMOS process. The DC power consumptions of the fabricated quadrupler core and input buffers are 6.4 mW and 28.8 mW, with power efficiency of 9% and 1.6%, respectively. This work has been presented at the 2012 International Solid-State Circuits Conference (ISSCC). Additional design considerations, i.e., effects of phase mismatch, and developments, such as the extension of concept to implement other multiplication factor, have also been conducted at such high frequencies.