VHDL synthesis of Montgomery modular multiplier

• Main Author: Sarasvathi Thangaraju.
• Other Authors: Chan, Choong Wah
• Format: Theses and Dissertations
• Published: 2008
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
• Online Access: http://hdl.handle.net/10356/3197
• Institution: Nanyang Technological University

This work describes the characteristics of two architectures designed to implement modular multiplication using the Montgomery Modular algorithm: the first FPGA design has an iterative sequential architecture while the second has a systolic array-based architecture. The first architecture proposed i...