VHDL synthesis of Montgomery modular multiplier

This work describes the characteristics of two architectures designed to implement modular multiplication using the Montgomery Modular algorithm: the first FPGA design has an iterative sequential architecture while the second has a systolic array-based architecture. The first architecture proposed i...

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Main Author:	Sarasvathi Thangaraju.
Other Authors:	Chan, Choong Wah
Format:	Theses and Dissertations
Published:	2008
Subjects:	DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
Online Access:	http://hdl.handle.net/10356/3197
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Institution:	Nanyang Technological University

id	sg-ntu-dr.10356-3197
record_format	dspace
spelling	sg-ntu-dr.10356-31972023-07-04T15:07:13Z VHDL synthesis of Montgomery modular multiplier Sarasvathi Thangaraju. Chan, Choong Wah School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits This work describes the characteristics of two architectures designed to implement modular multiplication using the Montgomery Modular algorithm: the first FPGA design has an iterative sequential architecture while the second has a systolic array-based architecture. The first architecture proposed in this work where Montgomery algorithm was implemented using an iterative design reduces the area usage in detriment of response time while the second architecture where Montgomery Modular Multiplication (MMM) was implemented using the systolic array reduces time response in detriment of area requirement. The speedup in modular computations using systolic array is due to the instantiation of components resulting in parallel computation. Master of Science (Integrated Circuit Design) 2008-09-17T09:24:26Z 2008-09-17T09:24:26Z 2005 2005 Thesis http://hdl.handle.net/10356/3197 Nanyang Technological University application/pdf
institution	Nanyang Technological University
building	NTU Library
continent	Asia
country	Singapore Singapore
content_provider	NTU Library
collection	DR-NTU
topic	DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
spellingShingle	DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits Sarasvathi Thangaraju. VHDL synthesis of Montgomery modular multiplier
description	This work describes the characteristics of two architectures designed to implement modular multiplication using the Montgomery Modular algorithm: the first FPGA design has an iterative sequential architecture while the second has a systolic array-based architecture. The first architecture proposed in this work where Montgomery algorithm was implemented using an iterative design reduces the area usage in detriment of response time while the second architecture where Montgomery Modular Multiplication (MMM) was implemented using the systolic array reduces time response in detriment of area requirement. The speedup in modular computations using systolic array is due to the instantiation of components resulting in parallel computation.
author2	Chan, Choong Wah
author_facet	Chan, Choong Wah Sarasvathi Thangaraju.
format	Theses and Dissertations
author	Sarasvathi Thangaraju.
author_sort	Sarasvathi Thangaraju.
title	VHDL synthesis of Montgomery modular multiplier
title_short	VHDL synthesis of Montgomery modular multiplier
title_full	VHDL synthesis of Montgomery modular multiplier
title_fullStr	VHDL synthesis of Montgomery modular multiplier
title_full_unstemmed	VHDL synthesis of Montgomery modular multiplier
title_sort	vhdl synthesis of montgomery modular multiplier
publishDate	2008
url	http://hdl.handle.net/10356/3197
_version_	1772828651806523392

VHDL synthesis of Montgomery modular multiplier

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