Design of a simple SRAM memory compiler using UMC 65nm
This thesis presents a full methodology of a Static Random Access Memory (SRAM) and steps to develop a simple SRAM memory compiler. The developed memory compiler is for general purpose and can be used in a field where the memory layout generators are required. Memory compilers are generally appli...
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| Format: | Final Year Project |
| Language: | English |
| Published: |
2013
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| Subjects: | |
| Online Access: | http://hdl.handle.net/10356/53399 |
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| Institution: | Nanyang Technological University |
| Language: | English |
| Summary: | This thesis presents a full methodology of a Static Random Access Memory (SRAM) and steps to develop a simple SRAM memory compiler. The developed memory compiler is for general purpose and can be used in a field where the memory layout generators are required.
Memory compilers are generally applied for custom DRAM and SRAM designs. For instance, a compiler consists of group of scripts and algorithms, which when compiled and executed, will generate a certain output layout based on the user inputs. While using the Cadence tools and PERL, the programming used as to develop the compilers.
The Memory compiler of SRAMs in this project was developed based on the layouts of the UMC 65nm technology. |
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