Design of a simple SRAM memory compiler using UMC 65nm
This thesis presents a full methodology of a Static Random Access Memory (SRAM) and steps to develop a simple SRAM memory compiler. The developed memory compiler is for general purpose and can be used in a field where the memory layout generators are required. Memory compilers are generally appli...
Saved in:
Main Author: | Emir Nurov |
---|---|
Other Authors: | Kim Tae Hyoung |
Format: | Final Year Project |
Language: | English |
Published: |
2013
|
Subjects: | |
Online Access: | http://hdl.handle.net/10356/53399 |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Institution: | Nanyang Technological University |
Language: | English |
Similar Items
-
A 65-nm 8T SRAM compute-in-memory macro with column ADCs for processing neural networks
by: Yu, Chengshuo, et al.
Published: (2022) -
Low power SRAM-based computing-in-memory design
by: Wang, Shuqi
Published: (2023) -
Design of SRAM-based in-memory-computing for machine learning applications
by: Ren, Mark
Published: (2023) -
Design of a 60-GHz voltage-controlled oscillator in 65nm CMOS
by: Wang, Haitao
Published: (2011) -
Design of SPST/SPDT switches in 65nm CMOS for 60GHz applications
by: He, Jin, et al.
Published: (2010)