Design of a simple SRAM memory compiler using UMC 65nm
This thesis presents a full methodology of a Static Random Access Memory (SRAM) and steps to develop a simple SRAM memory compiler. The developed memory compiler is for general purpose and can be used in a field where the memory layout generators are required. Memory compilers are generally appli...
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sg-ntu-dr.10356-533992023-07-07T16:26:28Z Design of a simple SRAM memory compiler using UMC 65nm Emir Nurov Kim Tae Hyoung School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering This thesis presents a full methodology of a Static Random Access Memory (SRAM) and steps to develop a simple SRAM memory compiler. The developed memory compiler is for general purpose and can be used in a field where the memory layout generators are required. Memory compilers are generally applied for custom DRAM and SRAM designs. For instance, a compiler consists of group of scripts and algorithms, which when compiled and executed, will generate a certain output layout based on the user inputs. While using the Cadence tools and PERL, the programming used as to develop the compilers. The Memory compiler of SRAMs in this project was developed based on the layouts of the UMC 65nm technology. Bachelor of Engineering 2013-06-03T03:49:15Z 2013-06-03T03:49:15Z 2013 2013 Final Year Project (FYP) http://hdl.handle.net/10356/53399 en Nanyang Technological University 42 p. application/pdf |
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DRNTU::Engineering::Electrical and electronic engineering Emir Nurov Design of a simple SRAM memory compiler using UMC 65nm |
| description |
This thesis presents a full methodology of a Static Random Access Memory (SRAM) and steps to develop a simple SRAM memory compiler. The developed memory compiler is for general purpose and can be used in a field where the memory layout generators are required.
Memory compilers are generally applied for custom DRAM and SRAM designs. For instance, a compiler consists of group of scripts and algorithms, which when compiled and executed, will generate a certain output layout based on the user inputs. While using the Cadence tools and PERL, the programming used as to develop the compilers.
The Memory compiler of SRAMs in this project was developed based on the layouts of the UMC 65nm technology. |
| author2 |
Kim Tae Hyoung |
| author_facet |
Kim Tae Hyoung Emir Nurov |
| format |
Final Year Project |
| author |
Emir Nurov |
| author_sort |
Emir Nurov |
| title |
Design of a simple SRAM memory compiler using UMC 65nm |
| title_short |
Design of a simple SRAM memory compiler using UMC 65nm |
| title_full |
Design of a simple SRAM memory compiler using UMC 65nm |
| title_fullStr |
Design of a simple SRAM memory compiler using UMC 65nm |
| title_full_unstemmed |
Design of a simple SRAM memory compiler using UMC 65nm |
| title_sort |
design of a simple sram memory compiler using umc 65nm |
| publishDate |
2013 |
| url |
http://hdl.handle.net/10356/53399 |
| _version_ |
1772829112055889920 |