32-bit adders using adiabatic switching for low power IC design
This dissertation describes the implementation of 32-bit adders using different adiabatic logic families. Adiabatic switching is a technique of power reduction where the energy taken from the power supply is recycled or reused. The adder is the most commonly used and critical arithmetic ope...
Saved in:
Main Author: | Joseph, Dhannya Mary |
---|---|
Other Authors: | Lau Kim Teen |
Format: | Theses and Dissertations |
Language: | English |
Published: |
2013
|
Subjects: | |
Online Access: | http://hdl.handle.net/10356/54906 |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Institution: | Nanyang Technological University |
Language: | English |
Similar Items
-
A full-custom IC design flow low power design using 16-bit full adder
by: Lim, Valerie Ying Fang.
Published: (2012) -
Low power 32-bit full adders in 65nm CMOS technology
by: Kumar, Praveen.
Published: (2014) -
16-bit full adder design based on cadence full-custom IC design flow
by: Yan, Aung Win
Published: (2012) -
A full-custom IC design flow high speed design using 16-bit full adder
by: Teo, Kok Xuan.
Published: (2012) -
Ultra-low power 8-bit CMOS adder design based on approximate arithmetic
by: Hu, Zhengyu
Published: (2019)