Cycle time optimization of semiconductor wafer fabrication system using simulation

Focuses mainly on batch size decision policies as part of cycle time optimization techniques. A simplified semiconductor wafer fabrication system model is built by using a simulation tool, ProModel. Then a particular product type is selected to run the simulation model.

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Bibliographic Details
Main Author:	Kyaw, Soe Nyunt.
Other Authors:	Sivakumar, Appa Iyer
Format:	Theses and Dissertations
Published:	2008
Subjects:	DRNTU::Engineering::Manufacturing::Production management
Online Access:	http://hdl.handle.net/10356/5920
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Institution:	Nanyang Technological University

id	sg-ntu-dr.10356-5920
record_format	dspace
spelling	sg-ntu-dr.10356-59202023-03-11T17:46:09Z Cycle time optimization of semiconductor wafer fabrication system using simulation Kyaw, Soe Nyunt. Sivakumar, Appa Iyer School of Mechanical and Production Engineering DRNTU::Engineering::Manufacturing::Production management Focuses mainly on batch size decision policies as part of cycle time optimization techniques. A simplified semiconductor wafer fabrication system model is built by using a simulation tool, ProModel. Then a particular product type is selected to run the simulation model. Master of Science (Computer Integrated Manufacturing) 2008-09-17T11:02:25Z 2008-09-17T11:02:25Z 2004 2004 Thesis http://hdl.handle.net/10356/5920 Nanyang Technological University application/pdf
institution	Nanyang Technological University
building	NTU Library
continent	Asia
country	Singapore Singapore
content_provider	NTU Library
collection	DR-NTU
topic	DRNTU::Engineering::Manufacturing::Production management
spellingShingle	DRNTU::Engineering::Manufacturing::Production management Kyaw, Soe Nyunt. Cycle time optimization of semiconductor wafer fabrication system using simulation
description	Focuses mainly on batch size decision policies as part of cycle time optimization techniques. A simplified semiconductor wafer fabrication system model is built by using a simulation tool, ProModel. Then a particular product type is selected to run the simulation model.
author2	Sivakumar, Appa Iyer
author_facet	Sivakumar, Appa Iyer Kyaw, Soe Nyunt.
format	Theses and Dissertations
author	Kyaw, Soe Nyunt.
author_sort	Kyaw, Soe Nyunt.
title	Cycle time optimization of semiconductor wafer fabrication system using simulation
title_short	Cycle time optimization of semiconductor wafer fabrication system using simulation
title_full	Cycle time optimization of semiconductor wafer fabrication system using simulation
title_fullStr	Cycle time optimization of semiconductor wafer fabrication system using simulation
title_full_unstemmed	Cycle time optimization of semiconductor wafer fabrication system using simulation
title_sort	cycle time optimization of semiconductor wafer fabrication system using simulation
publishDate	2008
url	http://hdl.handle.net/10356/5920
_version_	1761781384577286144

Cycle time optimization of semiconductor wafer fabrication system using simulation

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