Cycle time optimization of semiconductor wafer fabrication system using simulation
Focuses mainly on batch size decision policies as part of cycle time optimization techniques. A simplified semiconductor wafer fabrication system model is built by using a simulation tool, ProModel. Then a particular product type is selected to run the simulation model.
Saved in:
| 主要作者: | |
|---|---|
| 其他作者: | |
| 格式: | Theses and Dissertations |
| 出版: |
2008
|
| 主題: | |
| 在線閱讀: | http://hdl.handle.net/10356/5920 |
| 標簽: |
添加標簽
沒有標簽, 成為第一個標記此記錄!
|
| 機構: | Nanyang Technological University |