Cascade divide-by-two counter design for RFIC

• Main Author: Zhou, Hao
• Other Authors: Boon Chirn Chye
• Format: Final Year Project
• Language: English
• Published: 2014
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
• Online Access: http://hdl.handle.net/10356/60455
• Institution: Nanyang Technological University

Rapid evolution of the communication industry has increased the demand for RF circuits with higher speed performance and lower power dissipation. In the Phase Locked Loop (PLL) circuits which are frequently adopted as frequency synthesizer, the speed of frequency divider has become the bottlenecking element for the whole design. This project aims to analyze and compare the existing topologies as divider circuits as well as propose innovative designs to realize frequency division. The project focuses on high-frequency low-power cascade divide-by-two counter designs to achieve frequency division while many other alternative methods are not discussed in this project. Previous researchers have come up with various topologies in different CMOS technologies with different supply voltage, yet there lacks enough studies on cascade counter design. In this project, various divide-by-two topologies are studied and compared, simulations are done using 65nm CMOS technology at power supply of 1.0V. Both synchronous and asynchronous cascade divide-by-two counter designs are analyzed and compared. A combinational cascade divide-by-two counter design using both TSPC and CML topologies are proposed with a maximum operating frequency of 13.7GHz at power consumption of 20.153mW. Future studies could be done to further improve the performance of the combinational cascade divide-by-two counter in terms of reduction of noise, increase of sensitivity, and sharpen of waveform.