Mm-wave CMOS phase-locked loops

Due to the rapid development of Complementary Metal-Oxide-Semiconductor (CMOS) deep-submicron technology, the fT and fmax of CMOS transistors continue to rise, making the millimeter-wave (mm-wave or MMW) circuits implemented in CMOS technology becomes a reality. The challenges of mm-wave phase-locke...

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Main Author: Yi, Xiang
Other Authors: Boon Chirn Chye
Format: Theses and Dissertations
Language:English
Published: 2014
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Online Access:http://hdl.handle.net/10356/60476
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Institution: Nanyang Technological University
Language: English
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spelling sg-ntu-dr.10356-604762023-07-04T16:22:11Z Mm-wave CMOS phase-locked loops Yi, Xiang Boon Chirn Chye School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits Due to the rapid development of Complementary Metal-Oxide-Semiconductor (CMOS) deep-submicron technology, the fT and fmax of CMOS transistors continue to rise, making the millimeter-wave (mm-wave or MMW) circuits implemented in CMOS technology becomes a reality. The challenges of mm-wave phase-locked loop (PLL) design are high frequency, wide locking range, low phase noise, and low power. In recent years, many reported mm-wave PLLs in CMOS technology still face the problem of poor phase noise due to the low quality factor (low-Q) passive devices and noisy MOS transistors. Moreover, the power consumption of mm-wave PLL is a critical issue since the voltage-controlled oscillator (VCO) and the frequency divider (FD) become power-hungry in mm-wave frequency. Therefore, the focus of this thesis is not only on the PLLs but also on the VCOs and dividers. There are six contributions in my research. Firstly, an injection-locked frequency divider (ILFD), adopting a symmetrical injection circuit to generate the multi-phase injection with only single-phase input, was proposed. Secondly, an improved divide-by-2 ILFD which has differential inputs and quadrature outputs was designed. Thirdly, a mm-wave divide-by-2 current-mode logic (CML) divider followed by a divide-by-2 multi-phase injection ILFD was designed. Fourthly, a W-band varactor-less transformer-based VCO was proposed for imaging radar application. Fifthly, a low phase noise 24/77 GHz dual-band sub-sampling PLL with a dual-band VCO was proposed for automotive radar applications. Finally, the most important contribution of this thesis is that, a fully integrated 60 GHz frequency synthesizer with an in-phase injection-coupled quadrature voltage-controlled oscillator (IPIC-QVCO) was proposed for IEEE 802.11.3c application. Doctor of Philosophy (EEE) 2014-05-27T07:46:01Z 2014-05-27T07:46:01Z 2014 2014 Thesis Yi, X. (2014). Mm-wave CMOS phase-locked loops. Doctoral thesis, Nanyang Technological University, Singapore. http://hdl.handle.net/10356/60476 en 174 p. application/pdf
institution Nanyang Technological University
building NTU Library
continent Asia
country Singapore
Singapore
content_provider NTU Library
collection DR-NTU
language English
topic DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
spellingShingle DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
Yi, Xiang
Mm-wave CMOS phase-locked loops
description Due to the rapid development of Complementary Metal-Oxide-Semiconductor (CMOS) deep-submicron technology, the fT and fmax of CMOS transistors continue to rise, making the millimeter-wave (mm-wave or MMW) circuits implemented in CMOS technology becomes a reality. The challenges of mm-wave phase-locked loop (PLL) design are high frequency, wide locking range, low phase noise, and low power. In recent years, many reported mm-wave PLLs in CMOS technology still face the problem of poor phase noise due to the low quality factor (low-Q) passive devices and noisy MOS transistors. Moreover, the power consumption of mm-wave PLL is a critical issue since the voltage-controlled oscillator (VCO) and the frequency divider (FD) become power-hungry in mm-wave frequency. Therefore, the focus of this thesis is not only on the PLLs but also on the VCOs and dividers. There are six contributions in my research. Firstly, an injection-locked frequency divider (ILFD), adopting a symmetrical injection circuit to generate the multi-phase injection with only single-phase input, was proposed. Secondly, an improved divide-by-2 ILFD which has differential inputs and quadrature outputs was designed. Thirdly, a mm-wave divide-by-2 current-mode logic (CML) divider followed by a divide-by-2 multi-phase injection ILFD was designed. Fourthly, a W-band varactor-less transformer-based VCO was proposed for imaging radar application. Fifthly, a low phase noise 24/77 GHz dual-band sub-sampling PLL with a dual-band VCO was proposed for automotive radar applications. Finally, the most important contribution of this thesis is that, a fully integrated 60 GHz frequency synthesizer with an in-phase injection-coupled quadrature voltage-controlled oscillator (IPIC-QVCO) was proposed for IEEE 802.11.3c application.
author2 Boon Chirn Chye
author_facet Boon Chirn Chye
Yi, Xiang
format Theses and Dissertations
author Yi, Xiang
author_sort Yi, Xiang
title Mm-wave CMOS phase-locked loops
title_short Mm-wave CMOS phase-locked loops
title_full Mm-wave CMOS phase-locked loops
title_fullStr Mm-wave CMOS phase-locked loops
title_full_unstemmed Mm-wave CMOS phase-locked loops
title_sort mm-wave cmos phase-locked loops
publishDate 2014
url http://hdl.handle.net/10356/60476
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