Design of asynchronous microprocessor

• Main Author: Rajeindram, Brinthakumari
• Other Authors: Gwee, Bah Hwee
• Format: Final Year Project
• Language: English
• Published: 2014
• Subjects: DRNTU::Engineering
• Online Access: http://hdl.handle.net/10356/61000
• Institution: Nanyang Technological University

The paradigm of circuit design has shifted from synchronous design methodology to asynchronous design methodology due to various advantages brought about by asynchronous design principles. The advantages include reduced power dissipation and noise as well as increased circuit operating speeds. This final year project aims to study and investigate the feasibility of implementing the asynchronous framework using the Altera Quartus II circuit design and synthesis tools. The scope of the project includes the design and synthesis of the Pre-Charged Half Buffer (PCHB) Quasi-Delay Insensitive (QDI) Asynchronous Carry-Save Multipliers of word lengths 4-bit, 8-bit and 16-bit as well as the Bundled Data 4-Phase Asynchronous 32-bit MIPS processor.