Network design and characterization for ZedWulf

In recent times, we see an increasing amount of research interest in exploring the usage of ARM architectures in High Performance Computing (HPC). While pure ARM chips have historically been lacking the performance edge over x86, ARM-FPGA hybrid designs such as the Zynq SoC can be the potential cata...

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Main Author: Dhakshina Moorthy Pradeep
Other Authors: Nachiket Kapre
Format: Final Year Project
Language:English
Published: 2014
Subjects:
Online Access:http://hdl.handle.net/10356/61959
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Institution: Nanyang Technological University
Language: English
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spelling sg-ntu-dr.10356-619592023-03-03T20:30:11Z Network design and characterization for ZedWulf Dhakshina Moorthy Pradeep Nachiket Kapre School of Computer Engineering Centre for High Performance Embedded Systems DRNTU::Engineering In recent times, we see an increasing amount of research interest in exploring the usage of ARM architectures in High Performance Computing (HPC). While pure ARM chips have historically been lacking the performance edge over x86, ARM-FPGA hybrid designs such as the Zynq SoC can be the potential catalysts. In this project, we build a cluster composed of 32 such Zynq-based devices (Zedboards) to accelerate sparse-graph oriented problems, which are typically memory-bottlenecked on traditional x86 systems. We employ Message Passing Interface (MPI) to design an optimized scatter technique for supporting sparse-graph oriented irregular memory accesses across the cluster. We then formulate a performance model with a coefficient of determination more than 90% for understanding runtime scaling trends for our novel scatter-gather routine. We also run micro-benchmarks to understand Memory System, AXI – Accelerator Coherency Port (ACP) and Network characteristics of the Zedboard in the presence of Xillinux OS Bachelor of Engineering (Computer Engineering) 2014-12-12T04:07:32Z 2014-12-12T04:07:32Z 2014 2014 Final Year Project (FYP) http://hdl.handle.net/10356/61959 en Nanyang Technological University 22 p. application/pdf
institution Nanyang Technological University
building NTU Library
continent Asia
country Singapore
Singapore
content_provider NTU Library
collection DR-NTU
language English
topic DRNTU::Engineering
spellingShingle DRNTU::Engineering
Dhakshina Moorthy Pradeep
Network design and characterization for ZedWulf
description In recent times, we see an increasing amount of research interest in exploring the usage of ARM architectures in High Performance Computing (HPC). While pure ARM chips have historically been lacking the performance edge over x86, ARM-FPGA hybrid designs such as the Zynq SoC can be the potential catalysts. In this project, we build a cluster composed of 32 such Zynq-based devices (Zedboards) to accelerate sparse-graph oriented problems, which are typically memory-bottlenecked on traditional x86 systems. We employ Message Passing Interface (MPI) to design an optimized scatter technique for supporting sparse-graph oriented irregular memory accesses across the cluster. We then formulate a performance model with a coefficient of determination more than 90% for understanding runtime scaling trends for our novel scatter-gather routine. We also run micro-benchmarks to understand Memory System, AXI – Accelerator Coherency Port (ACP) and Network characteristics of the Zedboard in the presence of Xillinux OS
author2 Nachiket Kapre
author_facet Nachiket Kapre
Dhakshina Moorthy Pradeep
format Final Year Project
author Dhakshina Moorthy Pradeep
author_sort Dhakshina Moorthy Pradeep
title Network design and characterization for ZedWulf
title_short Network design and characterization for ZedWulf
title_full Network design and characterization for ZedWulf
title_fullStr Network design and characterization for ZedWulf
title_full_unstemmed Network design and characterization for ZedWulf
title_sort network design and characterization for zedwulf
publishDate 2014
url http://hdl.handle.net/10356/61959
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