Low power 16-bit multiplier design

• Main Author: Heng, Zeng An
• Other Authors: Gwee Bah Hwee
• Format: Final Year Project
• Language: English
• Published: 2015
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
• Online Access: http://hdl.handle.net/10356/62023
• Institution: Nanyang Technological University

The aim of this project is to investigate the design of different 16-bit CMOS Multiplier based on different logic and its implementation for portable low power applications. Arithmetic circuits such as digital adders and multipliers are used extensively in digital signal processor for filtering applications. In a digital multiplier, the addition of the partial products is normally carried out by a group of Half-Adders and Full-Adders. To reduce the delay and power dissipation of the multiplier, a 4-to-2 adder (comprises 2 Full-Adders) has recently been proposed to perform the partial product additions. In this project, the 16-bit CMOS multipliers architecture based on different types of adders will be investigated and developed using the VHDL code. The appropriate parameter values will be determined through behavioural simulations. The design could then be implemented into a FPGA for functional evaluation. Students will learn knowledge in IC design, Hspice, and VHDL code.