Performance analysis and comparison of low power dynamic and differential CMOS logic adder circuits

• Main Author: Prasanna Dhayalan
• Other Authors: Lau Kim Teen
• Format: Theses and Dissertations
• Language: English
• Published: 2015
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
• Online Access: http://hdl.handle.net/10356/65095
• Institution: Nanyang Technological University

Speed and density IC devices have seen exponential growth in the past few decades. Especially in energy constrained devices like laptops, mobiles and other portable devices improving the battery lifetime is a major challenge faced. By designing low power IC components, we can improve the overall battery life. Adder circuit is the critical component in any processor. The performance of the whole system depends upon Adder for a great extent. Thus, in order to reduce the power consumption of a Processor, it is necessary to design low power adder circuits. Several logic styles are available to design low power adder circuits. Dynamic and differential logic adders are significant because of their faster response and low power consumption. In my project, emphasis has been given on low power Dynamic and differential logic adders. They show better characteristics in terms of power consumption and response time. Several dynamic and differential logic styles are taken into study. Performance parameters: power consumption and delay time are measured and taken for my study. Dynamic and differential logic devices are compared with static CMOS, Pass transistor and hybrid CMOS logic adders and Data driven dynamic adder. All the simulations are done in Cadence environment using CSM 65nm CMOS technology.