2.5D and 3D I/O designs for energy-efficient memory-logic integration towards thousand-core on-chip

• Main Author: Sai Manoj Pudukotai Dinakarrao
• Other Authors: Yu Hao
• Format: Theses and Dissertations
• Language: English
• Published: 2015
• Subjects: DRNTU::Engineering::Computer science and engineering::Hardware::Input/output and data communications
• Online Access: https://hdl.handle.net/10356/65486
• Institution: Nanyang Technological University

In the past few decades, the design of computers has been primarily driven by improving performance with faster clock frequency of single-core processor using transistor scaling. The transistor scaling towards high performance of fast clock frequency is, however, stuck recently due to the constraint...