2.5D and 3D I/O designs for energy-efficient memory-logic integration towards thousand-core on-chip
In the past few decades, the design of computers has been primarily driven by improving performance with faster clock frequency of single-core processor using transistor scaling. The transistor scaling towards high performance of fast clock frequency is, however, stuck recently due to the constraint...
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| 格式: | Theses and Dissertations |
| 語言: | English |
| 出版: |
2015
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| 主題: | |
| 在線閱讀: | https://hdl.handle.net/10356/65486 |
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| 機構: | Nanyang Technological University |
| 語言: | English |