Floorplanning, power & area optimization for network-on-chip

• Main Author: Liauw, Javier Wei Sheng
• Other Authors: Gwee Bah Hwee
• Format: Final Year Project
• Language: English
• Published: 2016
• Subjects: DRNTU::Engineering
• Online Access: http://hdl.handle.net/10356/67985
• Institution: Nanyang Technological University

Multi-core System-on-Chips (SoCs) are a promising research area due to their improved speed (due to parallel processing) and possible higher energy-efficiency. Designing an SoC, realized by Network-on-Chip (NoC) is a promising research area applicable to many applications. The basic premises for NoC...