Floorplanning, power & area optimization for network-on-chip
Multi-core System-on-Chips (SoCs) are a promising research area due to their improved speed (due to parallel processing) and possible higher energy-efficiency. Designing an SoC, realized by Network-on-Chip (NoC) is a promising research area applicable to many applications. The basic premises for NoC...
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| 格式: | Final Year Project |
| 語言: | English |
| 出版: |
2016
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| 在線閱讀: | http://hdl.handle.net/10356/67985 |
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