16-bit low power multiplier design
Binary multipliers have been commonly used in many arithmetic circuits such that these multipliers are also mainly made up of half and full adders. Adders in the multiplier help to sum up the partial products and the carry bits in different levels depending on the bit size of the multiplier. In orde...
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| Format: | Final Year Project |
| Language: | English |
| Published: |
2016
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| Online Access: | http://hdl.handle.net/10356/68837 |
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| Institution: | Nanyang Technological University |
| Language: | English |
| Summary: | Binary multipliers have been commonly used in many arithmetic circuits such that these multipliers are also mainly made up of half and full adders. Adders in the multiplier help to sum up the partial products and the carry bits in different levels depending on the bit size of the multiplier. In order to minimize delay and power dissipation, Wallace Tree Algorithm (WTA) has been proposed to perform the partial product additions. For further improvement, Carry Lookahead Adder has been proposed for the final addition of the partial product in the final level. |
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