16-bit low power multiplier design
Binary multipliers have been commonly used in many arithmetic circuits such that these multipliers are also mainly made up of half and full adders. Adders in the multiplier help to sum up the partial products and the carry bits in different levels depending on the bit size of the multiplier. In orde...
Saved in:
| Main Author: | |
|---|---|
| Other Authors: | |
| Format: | Final Year Project |
| Language: | English |
| Published: |
2016
|
| Subjects: | |
| Online Access: | http://hdl.handle.net/10356/68837 |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| Institution: | Nanyang Technological University |
| Language: | English |
| id |
sg-ntu-dr.10356-68837 |
|---|---|
| record_format |
dspace |
| spelling |
sg-ntu-dr.10356-688372023-07-07T17:22:03Z 16-bit low power multiplier design Liew Tien Hong Gwee Bah Hwee School of Electrical and Electronic Engineering DRNTU::Engineering Binary multipliers have been commonly used in many arithmetic circuits such that these multipliers are also mainly made up of half and full adders. Adders in the multiplier help to sum up the partial products and the carry bits in different levels depending on the bit size of the multiplier. In order to minimize delay and power dissipation, Wallace Tree Algorithm (WTA) has been proposed to perform the partial product additions. For further improvement, Carry Lookahead Adder has been proposed for the final addition of the partial product in the final level. Bachelor of Engineering 2016-06-09T02:56:41Z 2016-06-09T02:56:41Z 2016 Final Year Project (FYP) http://hdl.handle.net/10356/68837 en Nanyang Technological University 37 p. application/pdf application/msword |
| institution |
Nanyang Technological University |
| building |
NTU Library |
| continent |
Asia |
| country |
Singapore Singapore |
| content_provider |
NTU Library |
| collection |
DR-NTU |
| language |
English |
| topic |
DRNTU::Engineering |
| spellingShingle |
DRNTU::Engineering Liew Tien Hong 16-bit low power multiplier design |
| description |
Binary multipliers have been commonly used in many arithmetic circuits such that these multipliers are also mainly made up of half and full adders. Adders in the multiplier help to sum up the partial products and the carry bits in different levels depending on the bit size of the multiplier. In order to minimize delay and power dissipation, Wallace Tree Algorithm (WTA) has been proposed to perform the partial product additions. For further improvement, Carry Lookahead Adder has been proposed for the final addition of the partial product in the final level. |
| author2 |
Gwee Bah Hwee |
| author_facet |
Gwee Bah Hwee Liew Tien Hong |
| format |
Final Year Project |
| author |
Liew Tien Hong |
| author_sort |
Liew Tien Hong |
| title |
16-bit low power multiplier design |
| title_short |
16-bit low power multiplier design |
| title_full |
16-bit low power multiplier design |
| title_fullStr |
16-bit low power multiplier design |
| title_full_unstemmed |
16-bit low power multiplier design |
| title_sort |
16-bit low power multiplier design |
| publishDate |
2016 |
| url |
http://hdl.handle.net/10356/68837 |
| _version_ |
1772826890342498304 |