Investigation of tradeoff between switching loss and EMI issue of gate driver with ferrite bead for SiC power module

• Main Author: Liu, Dongjie
• Other Authors: Tang Yi
• Format: Final Year Project
• Language: English
• Published: 2016
• Subjects: DRNTU::Engineering
• Online Access: http://hdl.handle.net/10356/69348
• Institution: Nanyang Technological University

It is well-known that gate driver design is a trade-off between switching loss and EMI issue. To maximize the high-efficiency, high-frequency benefits of SiC power devices, they need to be driven at high switching speed. However, the increasing dv/dt and di/dt ratios will tend to deteriorate this kind of EMI issue. Hence, the gate driver design becomes to be a new challenge for this newly emerging SiC power module. In this project, the high-speed gate driver is designed and optimized for SiC power module. And the ferrite bead is further introduced to mitigate EMI issue without compromise on switching loss. The general DPT circuit with clamped inductive load, which is usually used for switching characterization of power devices (shown at Figure 1.1). It can be used half bridge power module and also can be used as test discrete devices. The HS transistor MH is set to off all the time and the LS transistor ML will keep active, so that the dynamic characteristics of the MOSFET and its body diode can be obtained. If we use a freewheeling diode to instead of MH, this circuit will become a typical chopper. Then the dynamic characteristics of freewheeling diode can be obtained shown in Figure 1.2. But here is a pervasive problem associated to SiC devices, which is the effect of the parasitic parameters. Due to the oscillations during the switching transitions, this ringing will make the switching losses of the switching behavior increased. Furthermore, the conducted EMI and the radiated EMI will be much higher and the control signal will have more noise because of the generated oscillations due to the high frequency working environment. Refer to the previous researches, which suggest a proper layout of the gate driver is necessary, generally, in the direction of diminishing the parasitic inductance，the designer will place the driver as close as possible to the gate terminal, which is usually formed at the source and also at gate terminals in case of the SiC-MOSFET. Ferrite beads and RC snubbers were suggested being good ways to reduce the ringing by placing at the end of the terminal, which means putting at the gate of the MOSFET. For further information that is related to the effect of the ferrite beads and RC snubbers.