Failure analysis and characterization for microelectronic packaging
In the recent years, the mechanical robustness and reliability of three-dimensional (3D) integrated circuit (IC) packaging have become tremendously challenging due to its continuous reduction in size and increase in vertical integration. Thermal problems such as the silicon (Si) substrate cracking a...
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DRNTU::Engineering::Mechanical engineering Lin, Pamela Failure analysis and characterization for microelectronic packaging |
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In the recent years, the mechanical robustness and reliability of three-dimensional (3D) integrated circuit (IC) packaging have become tremendously challenging due to its continuous reduction in size and increase in vertical integration. Thermal problems such as the silicon (Si) substrate cracking and interfacial delamination are increasingly dominant due to the presence of high heat density in the small multilayer IC packaging. Furthermore, as the manufacturing and processing steps of the 3D ICs are significantly different from that of the conventional ICs, new defect and failure mechanisms that are unique to 3D ICs are not well-investigated. The reduction in size has also increased the sensitivity of the 3D ICs to microdefects that had not previously threatened their reliability and integrity. The increased complexity and miniaturization of 3D IC packaging and its consequential problems demand for new failure analysis methods. Therefore, this PhD research is proposed to study the physical failure modes and mechanisms associated with 3D ICs via molecular dynamics (MD) simulation and finite element method (FEM), and to develop new failure analysis methods for packaging characterization, thereby improving the packaging techniques and processes.
Si is commonly used as a substrate material in the IC packaging but yet its fracture behavior theoretical framework is still not well-developed. Thus, studies are first carried out on Si to understand its fracture mechanism through MD simulation and experiment. As the mechanical properties of Si are strongly influenced by the crystallographic orientation, defects, grain boundary (GB) and temperature, their effects on the tensile properties and failure mechanisms of Si are investigated. The results show that when Si is subjected to tensile loading, it undergoes brittle fracture and its (111) plane is the most favorable cleavage plane due to its high atomic packing density, thus resulting in the highest stiffness and lowest fracture strength. The presence of structural defects generally weakens the integrity of Si, particularly for the (100) oriented Si subjected to tensile loading in the [010] direction, its integrity is much more sensitive to these structural defects. The three-point bend test is also performed to investigate the crystallographic orientation and defects effects and the experimental results are found to be consistent with the MD results.
The investigation of ∑25(710)<010> tilt and ∑25(001)<001>twist GBs in bicrystal Si nanofilms show that their fracture strengths are lower than that of single-crystal Si, which is caused by the change in crystallographic orientation of the grains. It is observed that these nanofilms generally fail through sliding dislocation mechanism. The reduction in size results in the increase of surface effect, and thus less energy is required for dislocation sliding to occur at the surface. The strength is further weakened by the addition of notch at the free edge of the GB. The increase in temperature (up to 600 K) has insignificant influence on the failure mechanism but generally lowers the fracture strength as expected. These combined simulation and experimental findings are then used to substantiate and explain the fracture behavior of bulk Si subjected at the macroscale, thereby improving the accuracy of root cause analysis.
Furthermore, understanding and predicting interfacial delamination failure in the multilayered IC packaging are essential for their performance and reliability. The MD study is first performed to investigate the effect of voids and temperature on the interfacial fracture behavior in a-Si3N4/Si bilayer systems. When the bilayer system is subjected to tensile loading, its fracture behavior is found to be temperature-dependent. At 300 K, the interfacial strength of the bilayer system is ~22.5 GPa and it undergoes brittle fracture at the interface. However, failure occurs in the a-Si3N4 layer in a ductile mode when temperature is increased to 600K. With the existence of void in the Si layer in the a-Si3N4/Si system, crack initiates at the void and propagates towards the interface at 300 K. As the temperature increases to 600 K, the same bilayer system undergoes brittle fracture at the interface at a significantly lowered interfacial strength. With the inclusion of an interfacial void, the bilayer system fractures at the interface with a deteriorated strength regardless of the temperature. The simulation results also show that the presence of an interfacial void has a more adverse impact on the interfacial strength than having a void in the Si layer. Under the shear loading, the bilayer system deforms in three stages: elastic deformation, plastic flow in the a-Si3N4 layer and interfacial sliding. The presence of voids and the increase in temperature lower the stress required for interfacial sliding but they do not have significant effect on the shear deformation process.
Subsequently, a combined approach based on MD-FEM simulations is adopted to characterize and predict delamination in a-Si3N4/Si bilayer system. The material parameters that are required to be input into the cohesive constitutive relation in FEM are derived from MD simulation. The work of interfacial fracture obtained by the FEM simulation is about 0.11 J/m2 which is in good agreement with the experimentally obtained value of about 0.085 J/m2.
The above approach is also extended to characterize the interfacial energies and predict interfacial delamination in the Cu/Ti/SiO2/Si multilayered system. The thermodynamic work of adhesion W derived from MD simulation is used as the failure criterion for the FEM simulation as it is independent of the system geometry and applied strain rate. The interfacial fracture energy of 8.23 and 9.79 J/ m2 obtained from the MD-FEM simulations and the indentation damage experiment respectively, are also in good agreement. Hence, the combined approach is accurate and effective in characterizing and predicting the interfacial delamination in the multilayered IC packaging.
This PhD dissertation has investigated the fracture behaviour of bulk Si, bilayer systems and multilayered systems to understand their failure mechanisms and help in the failure analysis process. This study is able to provide useful information for 3D ICs design and applications and helpful in improving their stability and reliability. |
author2 |
Xu Huan |
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Xu Huan Lin, Pamela |
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Theses and Dissertations |
author |
Lin, Pamela |
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Lin, Pamela |
title |
Failure analysis and characterization for microelectronic packaging |
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Failure analysis and characterization for microelectronic packaging |
title_full |
Failure analysis and characterization for microelectronic packaging |
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Failure analysis and characterization for microelectronic packaging |
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Failure analysis and characterization for microelectronic packaging |
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failure analysis and characterization for microelectronic packaging |
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2017 |
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http://hdl.handle.net/10356/70126 |
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sg-ntu-dr.10356-701262023-03-11T18:04:40Z Failure analysis and characterization for microelectronic packaging Lin, Pamela Xu Huan Zhou Kun School of Mechanical and Aerospace Engineering Infineon Technologies Asia Pacific Pte Ltd DRNTU::Engineering::Mechanical engineering In the recent years, the mechanical robustness and reliability of three-dimensional (3D) integrated circuit (IC) packaging have become tremendously challenging due to its continuous reduction in size and increase in vertical integration. Thermal problems such as the silicon (Si) substrate cracking and interfacial delamination are increasingly dominant due to the presence of high heat density in the small multilayer IC packaging. Furthermore, as the manufacturing and processing steps of the 3D ICs are significantly different from that of the conventional ICs, new defect and failure mechanisms that are unique to 3D ICs are not well-investigated. The reduction in size has also increased the sensitivity of the 3D ICs to microdefects that had not previously threatened their reliability and integrity. The increased complexity and miniaturization of 3D IC packaging and its consequential problems demand for new failure analysis methods. Therefore, this PhD research is proposed to study the physical failure modes and mechanisms associated with 3D ICs via molecular dynamics (MD) simulation and finite element method (FEM), and to develop new failure analysis methods for packaging characterization, thereby improving the packaging techniques and processes. Si is commonly used as a substrate material in the IC packaging but yet its fracture behavior theoretical framework is still not well-developed. Thus, studies are first carried out on Si to understand its fracture mechanism through MD simulation and experiment. As the mechanical properties of Si are strongly influenced by the crystallographic orientation, defects, grain boundary (GB) and temperature, their effects on the tensile properties and failure mechanisms of Si are investigated. The results show that when Si is subjected to tensile loading, it undergoes brittle fracture and its (111) plane is the most favorable cleavage plane due to its high atomic packing density, thus resulting in the highest stiffness and lowest fracture strength. The presence of structural defects generally weakens the integrity of Si, particularly for the (100) oriented Si subjected to tensile loading in the [010] direction, its integrity is much more sensitive to these structural defects. The three-point bend test is also performed to investigate the crystallographic orientation and defects effects and the experimental results are found to be consistent with the MD results. The investigation of ∑25(710)<010> tilt and ∑25(001)<001>twist GBs in bicrystal Si nanofilms show that their fracture strengths are lower than that of single-crystal Si, which is caused by the change in crystallographic orientation of the grains. It is observed that these nanofilms generally fail through sliding dislocation mechanism. The reduction in size results in the increase of surface effect, and thus less energy is required for dislocation sliding to occur at the surface. The strength is further weakened by the addition of notch at the free edge of the GB. The increase in temperature (up to 600 K) has insignificant influence on the failure mechanism but generally lowers the fracture strength as expected. These combined simulation and experimental findings are then used to substantiate and explain the fracture behavior of bulk Si subjected at the macroscale, thereby improving the accuracy of root cause analysis. Furthermore, understanding and predicting interfacial delamination failure in the multilayered IC packaging are essential for their performance and reliability. The MD study is first performed to investigate the effect of voids and temperature on the interfacial fracture behavior in a-Si3N4/Si bilayer systems. When the bilayer system is subjected to tensile loading, its fracture behavior is found to be temperature-dependent. At 300 K, the interfacial strength of the bilayer system is ~22.5 GPa and it undergoes brittle fracture at the interface. However, failure occurs in the a-Si3N4 layer in a ductile mode when temperature is increased to 600K. With the existence of void in the Si layer in the a-Si3N4/Si system, crack initiates at the void and propagates towards the interface at 300 K. As the temperature increases to 600 K, the same bilayer system undergoes brittle fracture at the interface at a significantly lowered interfacial strength. With the inclusion of an interfacial void, the bilayer system fractures at the interface with a deteriorated strength regardless of the temperature. The simulation results also show that the presence of an interfacial void has a more adverse impact on the interfacial strength than having a void in the Si layer. Under the shear loading, the bilayer system deforms in three stages: elastic deformation, plastic flow in the a-Si3N4 layer and interfacial sliding. The presence of voids and the increase in temperature lower the stress required for interfacial sliding but they do not have significant effect on the shear deformation process. Subsequently, a combined approach based on MD-FEM simulations is adopted to characterize and predict delamination in a-Si3N4/Si bilayer system. The material parameters that are required to be input into the cohesive constitutive relation in FEM are derived from MD simulation. The work of interfacial fracture obtained by the FEM simulation is about 0.11 J/m2 which is in good agreement with the experimentally obtained value of about 0.085 J/m2. The above approach is also extended to characterize the interfacial energies and predict interfacial delamination in the Cu/Ti/SiO2/Si multilayered system. The thermodynamic work of adhesion W derived from MD simulation is used as the failure criterion for the FEM simulation as it is independent of the system geometry and applied strain rate. The interfacial fracture energy of 8.23 and 9.79 J/ m2 obtained from the MD-FEM simulations and the indentation damage experiment respectively, are also in good agreement. Hence, the combined approach is accurate and effective in characterizing and predicting the interfacial delamination in the multilayered IC packaging. This PhD dissertation has investigated the fracture behaviour of bulk Si, bilayer systems and multilayered systems to understand their failure mechanisms and help in the failure analysis process. This study is able to provide useful information for 3D ICs design and applications and helpful in improving their stability and reliability. Doctor of Philosophy (MAE) 2017-04-12T02:28:21Z 2017-04-12T02:28:21Z 2017 Thesis Lin, P. (2017). Failure analysis and characterization for microelectronic packaging. Doctoral thesis, Nanyang Technological University, Singapore. http://hdl.handle.net/10356/70126 10.32657/10356/70126 en 165 p. application/pdf |