Developing secure, ultra-low power RISC processor

• Main Author: Lim, Jun Hao
• Other Authors: Anupam Chattopadhyay
• Format: Final Year Project
• Language: English
• Published: 2017
• Subjects: DRNTU::Engineering::Computer science and engineering
• Online Access: http://hdl.handle.net/10356/70190
• Institution: Nanyang Technological University

General purpose Reduced Instruction Set Computing (RISC) processors are widely used while software applications are interacting with the Operating System (OS) to handle jobs, the OS communicate with the processor to complete the jobs with the help of accelerators. The goal of this project is to improve the area and speed of the processor while keeping the power usage to the minimum without compromising the security portion. The design of the processor and programming language will be based on an available open source RISC processor called RISC V, followed by an open source Hardware Description Language (HDL) named Chisel. By using HDL, the design of the processor will be explored at different levels to meet the goals as mentioned previously. For example, power consumption techniques like clock gating or and operand isolation will be introduced to minimize the power consumption and error correcting codes will be examined to tighten security. The final design will be synthesized into Zed Board Zynq 7000; a System on Chip development board for accurate benchmarking.