Compact modeling for GaN HEMT devices

• Main Author: Binit Syamal
• Other Authors: Zhou Xing
• Format: Theses and Dissertations
• Language: English
• Published: 2017
• Subjects: DRNTU::Engineering::Electrical and electronic engineering
• Online Access: http://hdl.handle.net/10356/70216
• Institution: Nanyang Technological University

This thesis presents a compact model developed for generic High Electron Mobility Transistors (HEMTs). The model is based on unified regional modeling (URM) of the 2-dimensional electron gas (2-DEG) charge density, including the two lowest sub-bands of the triangular well in the strong inversion region, and extending to the moderate inversion and subthreshold regions in a single-piece formulation. The 2-DEG charge density model is adopted in the surface-potential-based current/charge model for conventional bulk MOSFETs, which makes it compatible and scalable for future III-V/Si co-integrated technologies. HEMT-specific features are also included, such as nonlinear source/drain access resistances, self-heating, and parallel-channel effects. Apart from dc current/charge modeling, a comprehensive scalable trapcharge model for the dc and pulsed I–V modeling is also developed for GaNbased HEMTs, which suffer from current-collapse effects. A surface-potentialbased model is proposed for interface traps, which is then adapted to the current model for the dc trap modeling. For the pulsed I–V modeling, a semiempirical approach is used for gate-lag and drain-lag conditions. The trap-charge model captures the effects of gate and drain quiescent biases as well as the stress time, and is validated with both TCAD and measurement data. The final model is coded in Verilog-A and compared with transient simulations from TCAD, demonstrating gate-lag effects under switching operations. The methodologies presented in this thesis provide a broad platform for designing next generation III-V on Si co-integrated ultra-large scale integration systems for highfrequency applications.