Exploring network on chip strategies on FPGA

• Main Author: Tan, Kai Xiong
• Other Authors: Arvind Easwaran
• Format: Final Year Project
• Language: English
• Published: 2017
• Subjects: DRNTU::Engineering::Computer science and engineering
• Online Access: http://hdl.handle.net/10356/70448
• Institution: Nanyang Technological University

A configurable cycle-level Network-on-Chip (NoC) simulator is built in software framework. The software framework provides many NoC characteristic component that can be implemented in the NoC simulator. The software framework is written entirely in C++ programming language. Given the characteristics specification is defined, the NoC design can be implemented in the black box and tested for different scenarios and parameters. The software framework can be configured with varying combinations of processor and memory units. The NoC simulator can generate different traffic patterns and measure the average round-trip latency of a packet that is routed by the NoC design. The results of the simulation are displayed as a graph. The NoC design can also be converted into hardware design through Xilinx Vivado HLS (High-Level Synthesis) tool and implemented on a FPGA development board[1]. There are many different types of NoC implementations that have been published in the academic research. This report focus on real-time NoCs designs. It requires NoC to provide sufficient bandwidth and latency guarantees. “Statically scheduled TDM NoC” and “NOSTRUM” are implemented in the framework[2, 3]. The average round-trip latency is used for benchmarking the performance of the two NoC designs.